morph-ic data sheet revision 1.0 ? future technology devices international ltd 2004 morph-ic data sheet version 1.0 ? future technology devices international ltd 2004
morph-ic data sheet revision 1.0 ? future technology devices international ltd 2004 introduction morph-ic combines the fexibility of ftdis ft2232c usb interface i.c. together with an altera acex 1k series fpga ( ep1k10tc100-3 ) in a compact ready to use module. the power and io pins of the module are brought out onto 2 x 20pin, 0.1in pitch headers on the underside of the pcb , allowing easy connection to the pins on a 0.1in grid. the module can also be plugged into a pcb using readily available mating pcb connectors ( two included ). included on the module are the 3.3v and 2.5v voltage regulators required by the fpga as well as a 50mhz cmos oscillator hard wired to one of its two clock pins. power control to meet usb suspend current requirements is provided by the ft2232c and an on board mosfet power switch. morph-ic uses the multi protocol synchronous serial engine ( mpsse ) interface of the ft2232c to program / reprogram the fpga over usb in a fraction of a second. not only can the contents of the fpga be defned over usb on initialising the application software by loading them from an altera format confguration fle, but the contents of the fpga can be reloaded / redefned almost in real time ( under 0.2 seconds ). this effectively allows a single product to morph between different hardware confgurations under software control ( via usb ) from a single application. the second channel of the ft2232c is hard wired to the io pins of the fpga. these can be used by the fpga to communicate with the application software over usb at transfer rates of up to 1m byte / second. these features make morph-ic ideal for instrumentation, communications and other demanding application areas where fexibility and in-circuit hardware upgradability are of paramount importance. morph-ic comes complete with usb drivers for windows 98/me/2000/xp, vhdl code examples, fpga loader program ( including delphi source code ) and a windows dll interface which can be used to interface it to most common windows programming languages. examples of dll interfacing in visual c++, visual basic and borland delphi are provided. linux drivers and a linux version of the fpga loader written in kylix are also provided. an example project demonstrating io over usb is included complete with vhdl and delphi source code. to complete the package, a second cd contaning the quartus ii software starter suite is included. this contains the free altera quartus ii web edition software which provides a complete environment for programmable logic device (pld) design, including schematic- and text-based design entry, hdl synthesis, place-and-route, verifcation and simulation. this package runs under windows nt/2000/xp and can be used to develop code for the on-board fpga. registration with altera is required in order to run this package. morph-ics competitive pricing and quantity discount structure make it ideal for incorporating into low - medium volume designs. as it comes complete with all fpga development software required and example code it is also ideal as a classroom training tool for colleges and universities as well as engineers wanting to learn more about hardware development using fpgas. a range of optional training kits is under development which will allow students / engineers to study various areas of electronic engineering including a/d and d/a converters, video controllers and tv interfacing. training kits consist of an assembled pcb with all the components required for the projects into which you plug a morph-ic module ( extra ). training kits also come with a cd containing vhdl code and software source code for the projects in the kit. 3rd party contributions are also welcome - if you have a morph-ic project you would like to share with others please contact us.
morph-ic data sheet revision 1.0 ? future technology devices international ltd 2004 key features ? ft2232c dual usb uart / fifo i.c. ? altera acex? ep1k10tc100-3 fpga ? ultra fast fpga confguration / reconfguration over usb ( under 0.2 sec ) ? 576 embedded fpga logic elements ( == 10,000 gates typical ) ? 3 embedded logic ram / rom elements ( == 1.5k bytes memory ) ? fpga C pc usb data transfer at up to 1m byte/sec ? onboard 93c56 confguration eeprom ? mosfet switched 5v and 3.3v power outputs for powering external logic. ? onboard 6mhz crystal and essential support components for ft2232c. ? onboard 50mhz oscillator as fpga primary clock. ? onboard leds indicate usb driver enumeration and successful fpga device programming. ? 36 dedicated external io pins ? 8 shared external io pins ? 4 dedicated external input pins ? 1 dedicated external clock input ? powered from usb bus or external psu ? standard 0.1in pitch format connector pins, ideal for rapid prototyping and small-medium size production runs. ? ftdis vcp and d2xx usb windows and linux usb drivers ( provided ) eliminate the need for driver development in most cases. ? windows fpga loader interface dll supplied including interface examples in vb, vc++ and delphi. ? stand-alone fpga loader programs provided for windows and linux. ? vhdl programming examples ( i/o over usb ) provided. ? delphi application software examples including source code provided. ? morph-ic schematics provided. ? free altera quartus ii web edition development software included. figure 1 - morph-ic block diagram ( simplifed ) ft2232c usb interface i.c. usb connector gnd cn1 vcc(usb) vcc(5v) mosfet power switch 3.3v regulator vcc(3.3v) altera acex ep1k10tc-100 fpga 2.5v regulator vcore programming interface data transfer interface j1 j2 io connectors 50mhz oscillator ext clock ( pin 39 ) 93c56 usb configuration eeprom 6mhz xtal / resonator int clock ( pin 90 ) j2-14
morph-ic data sheet revision 1.0 ? future technology devices international ltd 2004 figure 2 ( left ) shows the location of the key components on the morph-ic module viewed from above. the module is connected to usb by plugging a usb a to b cable ( available separately ) into the usb type b connector shown at the top. fitting a jumper on jp1 selects usb bus powered mode ( the default ) where the module obtains its power from usb. to change the module to usb self powered mode, remove the jumper on jp1 and supply +5v from an external psu to j1 pin 1. the 93c56 eeprom is pre-programmed at the factory with the correct defaults for morph-ic operation. if re-programming this using ftdis mprog utility, great care must be taken or the module and its utilities may cease to work. two voltage regulators are provided on the module - the 2.5v regulator provides the power to the fpga core logic, whilst the 3.3v regulator provides power to the fpga io cells. the output of the 3.3v regulator is available through dedicated pins on j1 and j2 to supply up to 250ma of current to external logic. the 3.3v supply is switched off during usb suspend to conserve current. a 50mhz oscillator is provided on the module and is hard wired to clock pin 90 of the ep1k10tc- 100 fpga. for applications requiring a different clock frequency, use clock pin 39 of the fpga which is connected to j2 pin 14. a full listing of figure 2 - morph-ic key component location the pinouts of j1 and j2 is provided in figure 5. a 6mhz resonator on the module provides the master clock for the ft2232c. for detailed descriptions of the ft2232c and ep1k10tc-100, please consult the relevant data sheets. the ft22232c data sheet and application note can be found on the enclosed cd. the ep1k10tc-100 data sheet can be found on the altera web site at http://www.altera.com/literature/lit-acx.jsp figure 3 - morph-ic fpga programming interface ft2232c usb interface i.c. altera acex 1k ep1k10tc-100 fpga morph-ic fpga programming interface 24 23 22 21 20 16 75 76 51 25 1 79 dclk data0 nconfi g nstatus conf_done tck tdi tdo tms gpiol0 gpiol3 data3 mpsse interface
morph-ic data sheet revision 1.0 ? future technology devices international ltd 2004 ft2232c usb interface i.c. altera acex ep1k10-100 fpga morph-ic fpga data transfer interface 40 39 38 37 36 35 47 48 49 50 55 56 io io io io io bd0 bd1 bd2 bd3 bd4 bd5 io fifo interface 33 32 30 29 28 27 bd6 bd7 io io 57 58 61 62 63 64 io io io io rxf# txe# rd# wr 26 si/wub 65 io figure 3 shows the programming interface between the ft2232c and the ep1k10tc-100. it uses the multi-protocol synchronous serial engine feature ( mpsse ) of the ft2232c channel a to program the fpga on-the-fy. the fpga can be programmed / reprogrammed in under 0.2 seconds which makes it possible to design some type of products that would not normally ft into this size of fpga by using several different confguration fles for different modes of operation and loading / re-loading these transparently to the end-user. the confguration fles are output from the altera quartus ? software and can be downloaded into the fpga either manually by using the loader program supplied or under application software control by using the dll supplied. for further details of mpsse operation, consult the ft2232c data sheet and the application note an2232c-01 downloadable from ftdis web site at page http://www.ftdichip.com/ft2232c2.htm. the source code for the loader program and the dll illustrate how to program the mpsse as an altera acex series loader. morph-ic uses the gpiol0 pin of the ft2232c to detect / verify the completion of fpga device confguration and the gpiol3 pin of the ft2232c to provide a reset to the fpga via pin 79. figure 4 - morph-ic fpga data transfer interface figure 4 shows the bi-directional data transfer interface between the ft2232c and the ep1k10tc-100. it uses the fifo mode of the ft2232c channel b to allow the fpga to communicate with a pc over usb. data is read / written between the devices over an 8 bit data bus bd0 .. bd7. a typical application would send commands to the fpga which would be interpreted by a state machine inside the fpga. some commands may return data from the fpga to the application. to send data to the application poll txe# until it is low then place the data to be transmitted on bd0 .. bd7. enable the bus, strobe the wr pin high then low then disable ( tri-state ) the data bus pins. data is written into the ft2232c on the falling edge of wr. to receive commands / data from the application, poll rxf# until it is low which means that there is data in the ft2232c to be read. take rd# low to enable the data from the ft2232c on bd0 .. bd7. strobe the data into the fpga and make rd# high ( its default state ) to tri-state the bus. for further details of the ft2232c fifo mode including timings please consult the ft2232c data sheet. the example project on the cd illustrates such an application. full vhdl source code of the project and the delphi 5 application program are pubished on the cd and are a good starting point for developing morph-ic projects. note : the data bus and interface pins are all brought out on the j1 / j2 io connectors. the data bus can be used to send / receive data to other external devices when the ft2232c interface is in its idle state.
morph-ic data sheet revision 1.0 ? future technology devices international ltd 2004 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 morph-ic j1 pinout ( top view ) vcc(usb) io68 io71 vcc(3.3v) io69 resetin# gnd bc2 bc0 bd7 bd5 vcc(5v) gnd bc3 bc1 bd6 bd4 io85 io82 gnd vcc(3.3v) io84 io81 gnd io78 io80 io77 vcc(3.3v) io70 vcc(3.3v) io94 in89 gnd n/c io7 io86 in91 gnd io9 io6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 morph-ic j2 pinout ( top view ) bd3 in38 io32 vcc(3.3v) gnd clkin gnd io43 io46 n/c bd1 bd2 gnd in40 io45 n/c bd0 io26 io28 gnd vcc(3.3v) io23 io27 gnd io30 io31 io33 vcc(3.3v) io34 vcc(3.3v) io20 io22 gnd io16 io14 io21 io19 gnd io15 io13 figure 5 - morph-ic io connector pinout morph-ic has two dedicated 40 pin io connectors labelled j1 and j2. these are industry standard 40 pin connectors ( two rows of 20 pins ) with square pins on a 0.1in pitch. the two connectors are spaced 1.3in apart ( centre to centre ). see figure 6 for dimensional dr awings. the pinout of the connectors as viewed from above is shown in figure 5 and the pin descriptions are outlined in table 1, overleaf.
morph-ic data sheet revision 1.0 ? future technology devices international ltd 2004 morph-ic pin descriptions non-shared io pins io6, io7, io9, io13, io14, io15, io16, io19, io20, io21, io22, io23, io26, io27, io28, io30, io31, io32, io33, io34, io43, io45, io46, io68, io69, io70, io71, io77, io78, io80, io81, io82, io84, io85, io86, io94 these are io pins from the ep1k10tc100. the naming convention is ioxx where xx equals the pin number of the fpga. for example, io70 is the io pin on pin 70 of the device. shared io pins bd0(io47), bd1(io48), bd2(io49), bd3(io50), bd4(io55), bd5(io56), bd6(io57), bd7(io58) these are shared with the ft2232c data bus and can be used when the ft2232c data bus is in idle mode. see above notes on the ft2232c data transfer interface. dedicated input pins in38, in40, in89, in91 these are input pins from the ep1k10tc100. the naming convention is inxx where xx equals the pin number of the fpga. for example, in40 is the input pin on pin 40 of the device. all inputs are pulled up to 3.3v by an on- board 10k resistor. ft2232c handshaking bc0(rxf#), bc1(txe#), bc2(rd#), bc3(wr) these would not normally be connected to external logic, but are brought out for debug purposes i.e. for connecting a logic analyzer. clkin j2-14 secondary input clock source from pin 39 of the ep1k10tc100. resetin# j1-14 pulling this low resets the ft2232c i.c. and disconnects the device from the usb bus. not normally required but available if needed. pulled up to 5v by an internal 10k resistor. vcc ( usb ) ** note 1 j1-1 4.4v to 5.25v un-switched power from usb with j1 shorted. with j1 open, supply 5v power to this pin from an external power source. vcc ( 5v ) ** note 1 j1-2 power switched version of vcc (usb). power to this pin is turned off during usb suspend. vcc ( 3.3v ) ** note 1 j1-17, j1-18, j1-29, j1-31, j2-17, j2-18, j2-29, j2-31 3.3v ( +/-10% ) regulated power output. power switched version of vcc (usb). power to this pin is turned off during usb suspend. gnd j1-11, j1-12, j1-23, j1-24, j1-35, j1-36, j2-11, j2-12, j2-23, j2-24, j2-35, j2-36 gnd ( 0v ) power rail. n/c j1-37, j2-5, j2-6 these pins are not connected to anything on this version. do not use to ensure compatibility with future versions. table 1 - morph-ic io connector pinout description note 1 - the maximum combined current that can be drawn from these power sources to power external circuitry is 250ma in total. if a 5v supply is required, use vcc ( 5v ) instead of vcc ( usb ) to guarantee meeting usb current draw in usb suspend / sleep state ( < 0.5ma ).
morph-ic data sheet revision 1.0 ? future technology devices international ltd 2004 figure 6 - morph-ic dimensional information 0.2in 0.45in 0.43in 0.1in 0.1in 1.9in 0.065in 0.25in 0.35in 2.7in 1.6in cl 0.8in 0.5in 0.1in 0.1in 0.1in 0.1in
morph-ic data sheet revision 1.0 ? future technology devices international ltd 2004 document revision history dsmorphic version 1.0 C initial document created april 2004. disclaimer ? future technology devices international ltd, 2004 neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder . this product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. future technology devices international ltd. will not accept any claim for damages howsoever arising as a result of use or failure of this product. your statutory rights are not affected. this product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury . this document provides preliminary information that may be subject to change without notice. contact information future technology devices international ltd. 373 scotland street, glasgow g5 8qb united kingdom. tel : +44 ( 0 )141 429 2777 fax : +44 ( 0 )141 429 2758 e-mail ( sales ) : sales1@ftdichip.com e-mail ( support ) : support1@ftdichip.com ftdi web site url : http://www.ftdichip.com morph-ic web site url : http://www.morph-ic.com agents and sales representatives at the time of writing our sales network covers over 50 different countries world-wide. please visit the sales network page of our web site for the contact details of our distributor(s) in your country. trademarks morph-ic and the morph-ic logo are trademarks of future technology devices international ltd. acex 1k and quartus are trademarks of altera corporation. delphi is a trademark orf borland software corporation.
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